The present invention relates to compact electronic modules, and to components and packaging for use with such modules.
One of the long-term trends in electronics has been to provide higher functionality at lower cost in a more compact package. Many pages have been written on this long-term trend, and it will not be analyzed here. However, the numerous innovations disclosed in the present application are believed to contribute to a major advance in this direction.
Innovative Module
The present application discloses a very compact electronic module, which includes an integrated circuit (preferably including memory) and a battery. The module is preferably coin-shaped, and the two faces of the module are isolated from each other. Host systems can read/write access such modules, by using a one-wire-bus protocol.
One-Wire-to-Three-Wire Converter
The module may contain one integrated circuit or several, but the integrated circuits in the module preferably include a one-wire-to-three-wire converter circuit. In the presently preferred embodiment, this is integrated on a single chip with a small amount of serial-access memory. However, alternatively the converter may be used to provide a standard three-wire serial bus output, which provides an interface to one or more other chips. The other chips may include, for example, electronic keys (such as the DS1207 from Dallas Semiconductor).
ESD Protection Needs
A common specification for integrated circuits is the ability to withstand five successive electrostatic discharges (ESDs), each of 1000 volts, at the circuit pads, without the leakage current increasing to 1 micro Ampere. However, a de facto standard of 2000 V ESD immunity has been springing up for many applications.
However, even this level of ESD immunity may be insufficient for high-noise applications. Specifically, in the large-scale systems environment of the presently preferred embodiment, the data modules will face some unusual integrity requirements. Since the modules may be exposed to very rough treatment, in consumer and industrial environments, they should preferably have a very high level of immunity to electrostatic discharge (ESD).
The electronic data module of the presently preferred embodiment include an innovative ESD protection diode structure, which helps to protect against data loss under severe electrostatic discharge conditions.
Innovative Packaging Scheme
To fit the integrated circuit into this very small space, an innovative packaging scheme is used in the preferred embodiment. A two-part metal container is used, which has two shallow concave pieces which fit together. The integrated circuit (preferably in a low-height package, such as a flat-pack or small outline integrated circuit (SOIC) is mounted on a very small printed circuit board (preferably a flexible board), which fits inside the container. Laterally spaced from the integrated circuit, on the other end of the small board, the board end is sandwiched between a battery and a piece of elastic conductive material (such as conductive plastic foam). Thus, the battery is connected between one face of the container and a power conductor on the board. The piece of elastic conductive material makes contact between a data trace on the board and the other face of the container. Another trace on the board makes contact directly to the container face on which the battery's ground terminal is connected. Thus, simple wiring on the small board, using through-hole vias, suffices to route power, ground, and data lines to the integrated circuit, while providing a sealed durable package with two external contacts.
The battery is preferably a low-voltage battery (1.5 V, in the preferred embodiment.) This is cheaper, and maximizes power efficiency, but requires some innovative circuit design features to accommodate the electrical interface. (Electronic watches have often been powered by 1.5 V batteries, but such devices do not have any direct electrical interface to the outside world. By contrast, the module of the presently preferred embodiment communicates over a one-wire bus which is driven by full CMOS voltage levels.)
Module Mounting and Adhesion
The electronic token modules can be used in several ways. For example, in some embodiments it may be preferable it may be preferable to use loose tokens. However, in many applications (such as inventory control, machinery maintenance records, or retail tagging) it may be preferable to mount the tokens on the physical items to which the data in the individual tokens refers. In this case, the token must be mounted so that both terminals of the token can be contacted by the user. In the presently preferred embodiment (using a package like that shown in FIG. 1A), only one of the possible orientations will work. (The inner casing piece 100A must be exposed, and therefore, if the token is to be mounted on a surface, it is the outer casing piece 100B which should be adhered to the surface.)
For such applications, the packaged modules (in embodiments using packages like those of FIGS. 1A and 1B) are preferably shipped with double-sided adhesive tape already affixed to the side of the module which is to be adhered to a surface (face 100B, in the example of FIG. 1B).
Innovative Integrated Circuit
The module, in the presently preferred embodiment, contains an integrated circuit which itself includes several innovative features. This integrated circuit, in the presently preferred embodiment, includes an electrical interface to the one-wire bus (including heavy protection against minority carrier injection), a one-wire-to-three-wire converter circuit, and a small amount of serial-access memory.
The integrated circuit, in the preferred embodiment, contains 256 bits of serial-access memory. This memory is read- or write-accessed as a single block transfer. It is contemplated that larger amounts of memory may be advantageous. Of course, other types of memory organization can be used instead; but for many applications it is contemplated that use of a very small amount of memory (4K or less) may be particularly advantageous, since this extends the battery lifetime.
Low-Voltage SRAM Architecture
Among the innovative teachings set forth in the present application is a low-power low-voltage Complementary Metal Oxide Semiconductor (CMOS) six-transistor static random access memory (SRAM), which can operate on a power supply voltage which is less than the sum of the n-channel MOS (NMOS) and p-channel MOS (PMOS) threshold voltages, and which does not include any analog or metastable sense amplifier stages. The selected cell is allowed to pull one of its bitline pair all the way down to ground. Thus, full logic levels appear on the bitline pair. Only one line of the bitline pair is connected to the following gate stage. Preferably bitline precharge transistors are connected to pull up all bitline pairs whenever the RAM is not selected.
RAM/ROM Hybrid Memory
A further innovative teaching, in the preferred embodiment, is the use of RAM/ROM hybrid for a portion of the memory array. An innovative memory cell is used, which can operate as a static RAM, or which can be programmed to operate as a read only memory (ROM) cell. Thus users who need the extra security permitted by ROM encoding can have this capability, while users who do not need ROM encoding can use off-the-shelf parts as RAM only.
Chip Series with Unique Hard-wired Identifications
A further innovative large-scale system concept is to use the capability to introduce ROM into the memory space to provide memory chips with completely unique hard-wired identifications. This provides tremendous advantages for security-related needs.
In this embodiment, an external system can test the chip's integrity, by performing a read-write-read operation on the memory space which is supposed to be ROM, and also on a portion of the memory space which is expected to be RAM. This will provide at least some insurance against the ROM identification being emulated in RAM. Optionally, the external system can even test the data output timing, to ascertain whether the RAM and ROM outputs are timed identically (and therefore to assure that the address inputs are not being decoded to address two different chips).
This also provides advantages of failure protection. Very few catastrophes will be able to eradicate the hardware encoding of the cells which have been converted to ROM. (Even if the electrical functionality is totally destroyed, the fuse pattern can be read optically.) Thus, recovery of these bits may provide useful information in failure analysis. (For example, a manufacturing lot number can be cross-referenced from a unique identification number in ROM. This would provide greatly enhanced capabilities for analysis of late failures.
For another example, where the nonvolatility is electrically programmable, a system which recognized an imminent catastrophic failure (e.g. an avionics system facing a crash) might be able to save some data in the memory at the last minute.
Innovative ESD Protection Diode
The presently preferred embodiment uses an innovative protection diode structure, in which a significant device-level feature, is the provision of an intermediate-depth diffusion. This intermediate-depth diffusion will have a junction depth (inside the P-well or N-well) which is significantly deeper than the source/drain junction depth, but significantly shallower than the depth of the well. This intermediate-depth diffusion is useful in the innovative diode structure described, but can also be used for other device structures. For example, this structure provides a compact bipolar transistor structure with reasonably high gain. This intermediate-depth diffusion can also be used for input protection structures (i.e. to provide device structures which will rapidly and recoverably break down, when a high-voltage pulse appears, to discharge the high-voltage pulse without damaging the primary circuitry of the chip). For another example, this intermediate-depth diffusion can also be used to form diffused capacitors with relatively large capacitance per unit area, or capacitors whose capacitance varies greatly with voltage (such capacitors are commonly referred to as varactors.)
A further advantage of this structure, and a further innovative teaching set forth herein, is that the innovative structure can be fabricated with minimal added process complexity. An intermediate-depth diffusion is added to a standard process flow; but the shallow diffusions in the battery protection structure simply make use of the source/drain implants, and the deepest diffusion simply uses the N-well (or P-well) fabrication steps.
For process simplicity, the intermediate-depth diffusion is most preferably formed by using an implant which is identical (in dose and energy) to another implant used in the same process. The additional junction depth is achieved by exposing the earlier implant to a high-temperature step before the later implant is performed, so that the earlier implant will have a correspondingly greater diffusion length (integral (Dt).sup.0.5).
A variety of "substrate" structures are commonly used for integrated circuits, and far more have been proposed or have seen limited use. For example, the "substrate" which surrounds the N-wells and P-wells is often an eptaxial layer atop a much more heavily doped underlying layer. For another example, the N-wells and P-wells are commonly formed by separate implantation (and drive-in) steps, and such processes are referred to as "twin tub" processes; but alternatively one of these steps may be omitted, so that, for example, the PMOS devices might be formed directly in an N-type upper substrate portion. Other important structure types include silicon-on-insulator structures and full dielectric isolation structures, where there is no electrically continuous body linking all of the wells. It is important to note that the innovative teachings set forth herein can advantageously be adapted to a tremendous variety of substrate structures, including not only the embodiments listed or mentioned, but also many others.
It should be noted that the disclosed families of devices structures can also be used for a variety of other purposes. In particular, the disclosed structure provides a diode structure which may be adapted for use in other types of device structures, in very-low-power integrated circuit applications.
It should also be noted that some prior art CMOS structures have used guard ring structures to suppress latchup. The problem of latchup (suppressing the parasitic thyristor) is a quite different problem form the leakage problems discussed above, but in both cases collection of minority carriers is desirable. Guard ring structures are commonly used to surround locations (such as output drivers) where transient signals are most likely to cause injection of minority carriers. (A sufficient injection of minority carriers could fire the parasitic thyristor, and thus lead to latchup.)
In the preferred class of embodiments, the innovative diffusion structure described is used to conserve the charge in the battery. One drain on the battery is caused by negative excursions on an incoming data line (for example, when a negative voltage spike occurs due to an electrostatic discharge (ESD) event). In a normal battery-powered integrated circuit, the current drawn during such a negative voltage surge would be drawn both from the ground connection and also from the power supply connection. However, in stringently power-limited applications, even this amount of current, over the lifetime of the part, can use enough of the battery capacity to shorten the part's lifetime substantially.
That is, when a negative transient occurs, a large number of electrons will be injected. If these electrons are allowed to diffuse freely, many of them will diffuse toward the high-potential regions which are connected to the battery. This charge transfer reduces the total charge available during the lifetime of the battery.
The shielded diode structure of FIG. 16K is protected: almost all electrons injected at first junction 111 will be collected at second junction 112. By contrast, a simple field effect transistor (FET) output driver, like transistor 150 in FIG. 16M, is not isolated: when the drain junction of such an NMOS FET is forward biased, electrons will be released into substrate 140, and many of these electrons can then diffuse to regions of high potential.
Therefore, a further innovative teaching is to use the innovative diffusion structure to source current to negative transients which may occur on the I/O lines of a chip. In this embodiment, an I/O line is connected so that the first junction (in a structure as described above) will be forward biased when the I/O line goes negative, and the other side of the first junction is connected to ground potential. Thus, when a negative-going transient occurs, current will be sourced, through the first junction, from ground.
When a negative-going transient occurs, some current will also be sourced, at the output transistor which drives the I/O line, and some of this current component will cause minority carrier diffusion; but the use of this innovative teaching helps to reduce the amount of current sourced which can cause minority carrier diffusion. Preferably the area of the first junction is substantially larger than that of the junction area of the source/drain diffusion, in the output transistor, which is connected to the power supply.
This innovative teaching also has two further advantages. First, the reduced risk of minority carrier injection means that the risk of stored data states being upset by transient signals is reduced. Second, the risk of latchup is reduced.
Thus, this innovative teaching advantageously provides a battery-powered integrated circuit which is protected against battery depletion by electrical noise appearing at input/output connections. This innovative teaching may be particularly advantageous in integrated circuits which are intended for use in systems where high levels of noise must be tolerated.
Innovative Bus Organization
To communicate with this memory, in the preferred embodiment, an innovative one-wire bus protocol is used. This protocol is well adapted for interface to the low-cost architecture of the module of the presently preferred embodiment.
Time-Domain Relations
A bidirectional one-wire bus requires some use of time-domain or frequency-domain relations, to track the two half-channels of communication.
It is quite possible to put an accurate time base in a low-power integrated circuit, using CMOS oscillators stabilized with quartz crystals; but the use of such techniques adds to the cost of the part. A crude time base can be provided simply by using an oscillator which is not stabilized. However, the response time of a simple timing circuit will be dependent on processing parameters. In conventional integrated circuit processing, there will normally be significant variation in parameters such as layer thickness, line-to-space ratio, and net dopant concentration in various locations. Thus, the electrical parameters, such as the series resistance of a polysilicon resistor of a given nominal dimension, can easily vary by .+-.20% or more, even in a well-controlled process. This means that the net speed of a timing circuit can vary by even more, since the net speed will be dependent on several electrical parameters, which may vary together or in opposition.
Parameter variation can be compensated for, by testing a newly fabricated wafer and programming elements on-chip (such as trimming capacitors) to adjust the net delay of timing elements; but this additional manufacturing step adds significant expense.
Low-Voltage CMOS Logic
Moreover, in a low-voltage CMOS system (i.e. where the supply voltage is less than the sum of the PMOS and NMOS threshold voltages), achieving even a crude time base is much more difficult. This is due to the transfer characteristics of a logic gate in this technology.
FIG. 5A shows the voltage transfer characteristics (V.sub.OUT graphed as a function of V.sub.IN) for an inverter in conventional CMOS technology (e.g. where the supply voltage V.sub.DD is about 5 Volts, and the PMOS threshold voltage V.sub.TP and the NMOS threshold voltage V.sub.TN both have magnitudes in the range of about 0.8 V to 1.1 V.) Suppose that the input voltage V.sub.IN was initially at ground voltage V.sub.SS (0 V), so that the inverter's NMOS transistor is off and the inverter's PMOS transistor is on. Now, as V.sub.IN starts to rise, V.sub.OUT will stay at V.sub.DD until V.sub.IN rises to V.sub.TN. At this point the NMOS device will start to pass current. However, the NMOS device will not be able to overpower the PMOS device until the voltage reaches a trip point V.sub.TRIP. The trip point voltage V.sub.TRIP is well-defined for each particular logic gate, but is dependent on the device dimensions. (If the width of the PMOS device is increased, or the length of the PMOS device decreased, or the width of the NMOS device is decreased, or the length of the NMOS device increased, then the NMOS device will have more difficulty in overpowering the PMOS device, and the trip point V.sub.TRIP will occur at a higher voltage.) As the input voltage V.sub.IN increases, the NMOS device will pass more current and the PMOS device will pass less current, until at voltage V.sub.DD -V.sub.TP the PMOS transistor turns off.
By contrast, the transfer characteristic of a low-voltage CMOS inverter, as shown in FIG. 5B, are quite different. (Suppose, for example, that V.sub.DD =1.5 V, and V.sub.TP =V.sub.TN =0.9 V. Thus, note that FIGS. 5A and 5B are not drawn to the same scale.) Here there is no region where both the NMOS and PMOS devices are on. When the input voltage V.sub.IN increases above V.sub.DD -V.sub.TP (0.6 V in this example), the PMOS device will turn off, but the NMOS device has not yet turned on. Therefore, until the input voltage increases to V.sub.TN (0.9 V in this example), the output node will be floated. (The node capacitance usually faces a fairly high-impedance load, and therefore, within the time normally required for the input voltage to swing across this voltage range, the output voltage will remain fairly constant. Moreover, a weak latch will typically be added to bridge this dead zone.) Thus, the transfer characteristic shown includes a significant hysteresis, since, between V.sub.DD -V.sub.TP and V.sub.TN, the output voltage is dependent on the direction of change of the input voltage.
Error of Crude Time Base
A response curve like that of FIG. 5B makes it more difficult to control the net delay of a circuit, since small changes in electrical parameters may produce large changes in the response characteristics. Thus, in such low-voltage technology, the frequency of an unstabilized oscillator may easily vary over a very large range (for example, over a range of 4:1), even in a well-controlled process.
The system of the presently preferred embodiment makes use of such an unstabilized oscillator to provide a crude time base within the module. This crude time base, together with electrical relationships, provides the necessary referent for communication over a one-wire bus. The use of a one-wire bus is very advantageous to the system user.
Electrical I/O Relationships
The bus protocol is also designed to minimize the charge transfer out of the battery in the module. This is done by using an "open-collector" type architecture. The protocol has been specified so that the module never sources current to the data line, but only sinks current.
When a data module is in contact with a host system, the host system initially pulls up the data line. (The module also preferably contains a very high-impedance pull-down resistor at this node, but this is included, in the preferred embodiment, merely to avoid the risk of floating nodes.) The host system initiates each stage of a data transfer operation by driving the data line low. The module detects this falling edge, and one of several further events can then occur.
If the module is being read (as previously determined by overhead bits), the module, after seeing the falling edge which starts the cycle, either will or will not turn on its NMOS pull-down transistor, depending on the value of the data bit being read at that cycle. When the NMOS pull-down is turned on, the module lets its preset timing period elapse, and then turns off the NMOS pull-down. Thus, when the system wants to read from the module, it applies a falling edge, waits a short time to be sure that the module has received the falling edge, and then attempts to pull up the data line, using a pull-up resistor which is not strong enough to overpower the NMOS pull-down transistor in the module. After waiting a sufficient time for the pull-up resistor to have raised the line to a high level (if the NMOS pull-down is off), the system tests the data voltage to ascertain the data bit. The system then waits for the maximum time period of the module delay to elapse, plus enough time for the data line to stabilize at a high level, and then sends another falling edge to read the next bit.
If the module is being written to (as previously determined by the overhead bits), the module, after seeing the falling edge which starts the cycle, waits for its preset timing period to elapse, and then stores the logic value of the data line. Thus, when the system wants to write to the module, it applies a falling edge, waits a short time to be sure that the module has received the falling edge, and then drives the data line either high or low, depending on the data bit. The system then waits for the maximum time period of the module delay to elapse, restores the data line to a high level, allows enough additional time for the data line to stabilize at a high level (and for the edge detector in the module to reset itself), and then sends another falling edge to write the next bit.
Block Transfer--Overhead and Reset
All data transfers are preferably done by reading or writing the entire contents of memory as a single serial stream. A short block of overhead bits, at the start of each transfer, defines the transfer type.
A further point of the protocol is a way to reset the module. Suppose, for example, that a module is pulled out of the slot in the middle of a data transfer, so that the memory pointer inside the module shows that the next bit to be written is bit number 117. The next system into which this module is inserted must not assume that the module's starting address is necessarily zero.
To make sure that the starting memory address of a newly inserted module is zero, as expected, the system sends a long string of write-zero commands, followed by a write-one command. The module contains simple sequential logic, which monitors the incoming bit stream for nonstop sequences of write-zero commands. If the module receives a nonstop sequence containing as many write-zero commands as the total length of the memory, the counter will freeze until the chip is reset. The chip will be reset if and only if an incoming "1" bit is seen while the counter is frozen.
This provides a reset capability, whereby the system can ensure that the starting address of the module is accurately known. Thus, on every insertion of a new module, the system can send such a reset sequence to initialize the address pointer in the module. Note that this address-pointer-reset is only necessary once per insertion. The sequence of write-zero commands will not normally destroy data, because the module never receives the overhead bit sequence which would tell it to enter write mode. (The only conditions under which data could be destroyed by these commands is when the module has been interrupted in the middle of a previous write sequence, and in this case the data may be presumed corrupt anyway.)
Of course, the data structures inside memory would normally include provisions for software error protection, such as overhead bits and checksum bits. However, a wide variety of such formatting schemes can be used, at the discretion of the user.
Innovative System Architecture
These innovative ideas are used as parts of a very innovative system architecture. The electronic module enabled by the innovative teachings herein is extremely compact and extremely cheap. From a systems point of view, this module is in some ways more analogous to a read/write bar code than to a conventional electronic memory system.
Macro-System Architecture
Thus, this innovative module can be used for price tags, for inventory tags, for work-in-process monitoring, for retail sales (to permit customers to select merchandise (e.g. by taking one module or a handful of modules to a cashier or to an automated check-out machine), without exposing the actual inventory to pilferage), and for a wide variety of other such compact data-transfer applications. Thus, the innovative module described can be regarded as an electronic token, which is as portable and rugged as a metal token, but which is far more versatile.
This provides an innovative large-scale systems architecture, wherein multiple host systems can each interface to small electronic "tokens." The tokens are small coin-shaped two-terminal read/write data modules, and are compact, rugged, and extremely cheap. Each of the tokens contains only two external contacts, a battery, and a small amount of memory. The memory is serially accessible, using a one-wire-bus protocol which minimizes the drain on the battery.
Electrical Interface from Token to Standard RS232 Interface
The presently preferred embodiment also uses an innovative electrical interface to the tokens, which permits interfacing to tokens with a wide variety of computers, including a tremendous variety of personal or other computers, as long as the computer includes an interface to RS232 (or some comparable standard). The token has a one-wire-bus interface, implemented in a battery-backed open-collector architecture, which provides a read/write interface. The communication protocol expected by the token has been specified so that the token never sources current to the data line, but only sinks current. The communication protocol also includes time-domain relations which are referenced to a very crude time base in the token, and the system must preserve timing relations which will be satisfied by tokens in which the time base takes on any of the wide range of foreseeable speeds. To interface to this protocol, the programmable capabilities of the standard UART chip in the computer's RS232 interface are exploited to provide adaption to the time base requirements of the module. This is done by writing an entire byte of output from the UART, at a much higher baud rate than the module can be relied on to accept, to write a single bit of data into the module. The read-data line (RX) of the UART is tied back to the transmit-data line (TX) through a resistor, so that the UART will also always report a read of the same data byte being written, unless the token has turned on its pull-down transistor. An electrical network is used at the interface which (in effect) reverses the ground plane identification of the two leads, but which does provide the correct signal polarity to the token for signal discrimination in read mode.
Physical Interface for Receiving Electronic Tokens
Preferably each host system uses a physical configuration of electrical contacts which provides rapid contact for electronic data modules (tokens). A slot, dimensioned to receive electronic tokens, includes a grounded contact positioned to make contact to the edge of a token which may be inserted, and two data contacts which are positioned to make contact to the opposite faces of the token. Each of the data contacts is connected to an open-collector driver circuit, including a pull-up resistor which will bring the potential of the contact high when the slot is empty. The token is shaped so that its edge, and one of its faces, are connected to the token's ground line, and the other face is the token's data line. Thus, when a token is inserted (no matter which way the token is facing), one of the two data contacts will be immediately pulled to ground, by short-circuiting across the ground plane of the token. The system can thereby recognize that a token has been inserted, and that the other data contact (the one which was not shorted to ground) can communicate with this token's data line. Thus, even though the token itself is asymmetric, and even though the directional orientation of the token is not initially known to the system, no physical asymmetry needs to be introduced into the token or the slot to assure proper data interface.
Alternative Physical Interface - Hand-Held Wand
A wand which provides rapid contact to a two-terminal electronic token data module. The wand includes one contact which will make contact to the periphery of an electronic token which the wand is pressed against, and one contact which will make contact to the center of the token. Preferably the wand includes a base portion which is shaped to be worn on the second joint of a user's finger. This wand can be used for very rapid manual contacting of electronic tokens in various physical positions. This can be very advantageous in a variety of data collection/updating applications such as retail checkout, or tracking work-in-progress in a computer-assisted-manufacturing environment.